module mac_rec_01(
		input	wire		resetb,

		input	wire		rx_clk,
		input	wire		rx_dv,
		input	wire	[7:0]	rx_data,		
			
		output	reg		mac_flag,
		output	reg	[7:0]	mac_data,

		output  wire	[23:0]	tout                               
		);

reg		rec_start;
		
always @(posedge rx_clk or negedge resetb)
	if (resetb==0)
		mac_data<=0;
	else
		mac_data<=rx_data;

always @(posedge rx_clk or negedge resetb)
	if(resetb ==0)
		rec_start<= 0;
	else if (mac_data==8'h55 && rx_data==8'hd5)
		rec_start<= 1;
	else
		rec_start<=0;
		
always @(posedge rx_clk or negedge resetb)
	if(resetb ==0)
		mac_flag<= 0;
	else if (rx_dv==0)
		mac_flag<= 0;
	else if (rec_start==1)
		mac_flag<=1;

assign	tout=0;

endmodule
